1. Field of the Invention
The present invention relates to a semiconductor integrated circuit with a voltage adjusting circuit for generating a voltage corresponding to an input voltage.
2. Description of the Background Art
Recently, with the development in the field of information and communications, the prevalence of mobile communication devices such as a mobile phone is prominent. Under such circumstances, the requirement for reducing power consumption of semiconductor integrated circuits, which are employed in such devices, is ever increasing. Among others, in a DRAM (Dynamic Random Access Memory) circuit included in the mobile communication device, a standby state in which no input occurs lasts for a long period. Attempts have been made for reducing the power consumption during the standby state, by adjusting the cycle of so-called self-refresh operation for retaining data during the standby state.
The self-refresh operation is performed as follows: the address of the object to be refreshed is internally generated automatically, and address selection is performed automatically within the DRAM circuit. Further, in response to refresh clock signals periodically generated by an internal refresh timer, the refresh operation is successively performed on prescribed refresh cycle basis.
FIG. 15 illustrates the arrangement of a ring oscillator circuit for generating refresh clock signals.
The ring oscillator circuit has (2n+1) inverters IV (where n is a natural number) connected in series. In FIG. 15, one example is shown where n=3. These inverters are connected in a ring arrangement, with an output of an inverter of the last stage fed back to an input node of an inverter of the first stage. This ring oscillator circuit supplies to the internal circuit refresh clock signals at oscillation frequency corresponding to the operating current of the inverter.
All of the inverters IV have the same arrangement, thus inverter IV of the first stage will be described as a representative. Inverter IV includes transistors PT, NT and NTT. Transistor PT is provided between power supply voltage VCC and node Nd, and receives at its gate an input signal of external clock signal ext.CLK. Further, transistor NT is provided between ground voltage GND via transistor NTT and node Nd, and receives at its gate an input signal of external clock signal ext.CLK. Transistor NTT is serially connected to transistor NT between node Nd and ground voltage GND, and receives at its gate an output voltage from a voltage adjusting circuit 300. As an example, transistor PT is a P-channel MOS transistor. Further, as an example, transistors NT and NTT are N-channel MOS transistors.
Inverter IV complementarily turns transistors PT and NT on in response to the input signal of external clock signal ext. CLK, and supplies to inverter IV of the next stage the voltage level corresponding to the input signal. Here, the gate of transistor NTT receives output voltage Vout generated by voltage adjusting circuit 300 as described above. Thus, operating current of inverter IV is adjusted by voltage adjusting circuit 300. Accordingly, the ring oscillator circuit generates refresh clock signals at oscillation frequency corresponding to the voltage level of the output voltage generated by voltage adjusting circuit 300.
FIG. 16 shows circuit arrangement of voltage adjusting circuit 300 used in the ring oscillator circuit.
Referring to FIG. 16, voltage adjusting circuit 300 includes transistors 301 to 304.
Transistor 301 is provided between a voltage node supplied with power supply voltage VCC and node Na, and has its gate electrically coupled with node Na. Transistor 302 is provided between a voltage node supplied with power supply voltage VCC and output node Nb, and its gate is electrically coupled with node Na. Transistor 303 is provided between ground voltage GND and node Na, and receives at its gate the input signal of input voltage Vin. Transistor 30.4 is provided between output node Nb and ground voltage GND, and receives at its gate input of output node Nb. Here, as an example, transistors 301 and 302 are P-channel MOS transistors. Further, as an example, transistors 303 and 304 are N-channel MOS transistors.
The voltage adjusting circuit generates a constant voltage Vout in response to input voltage Vin by a current mirror formed with transistors 301 and 302. The voltage level of constant voltage Vout is set depending on the size of each of the transistors forming voltage adjusting circuit.
Accordingly, by adjusting output voltage of the voltage adjusting circuit, the refresh operation can normally be performed at accurate cycle.
The refresh cycle of performing refresh operation is determined by the time during which memory cells can retain data, i.e., the data retention period, which in turn depends on leakage current of memory cells. In memory cells sensitive to the variations in temperature, the leakage current of memory cells increases almost three orders of magnitude when temperature rises by 100° C. Therefore, the refresh cycle must properly be set corresponding to the temperature.
On the other hand, since the voltage level of the output voltage of the voltage adjusting circuit above will be the value set corresponding to the size of transistor in the arrangement, the voltage level can not be adjusted corresponding to the variations in the temperature.
Accordingly, when the voltage adjusting circuit is applied to a ring oscillator circuit, for example, the refresh cycle can not properly be adjusted internally. Thus, in order to ensure data retention characteristics of memory cells under high temperatures, the voltage adjusting circuit has been designed to have refresh cycle matched to the performance thereof under high temperatures. Therefore, the refresh operation has been performed with excessive frequency for room temperature or low temperatures, which unnecessarily increases power consumption for refresh operation.